 |
| Total: 95 |
| Meng-Jai
Tasi, Chia-Tso Chao, Jing-Yang Jou, and Meng-Chen Wu, "Multiple-Fault
Silicon Diagnosis Using Faulty-Region Identification", IEEE VLSI Test
Symposium 2009, May 2009. |
| Liang-Yu
Lin, Huang-Kai Lin, Cheng-Yeh Wang, Lan-Da Van and Jing-Yang Jou,
"Hierarchical Architecture for Network-on-Chip Platform", IEEE
International Symposium on VLSI Design, Automation, and Test
(2009 VLSI-DAT) , April 2009. |
| Kuang-Chin
Cheng and Jing-Yang Jou, "Crosstalk-Avoidance Coding for Low-Power
On-Chip Bus", The 15th IEEE International Conference on Electronics,
Circuits and Systems , Malta, September 2008. |
| Geeng-Wei
Lee, Juinn-Dar Huang, Jing-Yang Jou, Floorplan-Aware Design Methodology
for Application-Specific Bus Matrix Systems, The 14th Workshop on Synthesis
And System Integration of Mixed Information technologies" (SASIMI2007),
October 2007. |
| Tzu-Wei
Lin, Shang-Wei Tu and Jing-Yang Jou, On-Chip Bus Encoding for Power Minimization
under Delay Constraint, IEEE International Symposium on VLSI Design,
Automation, and Test (2007 VLSI-DAT) , April 2007. |
| Bu-Ching
Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, A Precise Bandwidth
Control Arbitration Algorithm for Hard Real-Time SoC Buses, The 12th
Asia and South Pacific Design Automation Conference (ASP-DAC2007), January
2007. |
| Chun-Ming
Huang, Kuang-Jong Lee, Chih-Chyau Yang, Wen-Shiang Hu, Shi-Shen Wang,
Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai
and Jing-Yang Jou, Multi-Project System-on-Chip (MP-SoC): A Novel Test
Vehicle for SoC Silicon Prototyping, 2006 IEEE International SOC Conference
(2006 SOCC), September 2006 (Invited). |
| Man-Yun
Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou, FSM-Based Transaction-Level
Functional Coverage, The 11th Asia and South Pacific Design Automation
Conference (ASP-DAC2006), January 2006. |
| Chien-Hua
Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, A Real-Time and
Bandwidth Guaranteed Arbitration Algorithm for SoC Bus Communication,
The 11th Asia and South Pacific Design Automation Conference (ASP-DAC2006),
January 2006. |
| Che-Hua
Shih, Juinn-Dar Huang, and Jing-Yang Jou, Stimulus Generation for Interface
Protocol Verification Using the Non-Deterministic Extended Finite State
Machine Model, 10th IEEE International High Level Design Validation and
Test Workshop (HLDVT 2005), November 2005. |
| Chia-Chih
Yen and Jing-Yang Jou, "An Optimum Algorithms for Compacting Error
Traces for Efficient Design Error Debugging, 10th IEEE International
High Level Design Validation and Test Workshop (HLDVT 2005), November
2005. |
| T.Y. Jiang,
C. N. Liu, and J. Y. Jou, Estimating Likelihood of Correctness for Error
Candidates to Assist Debugging Faulty HDL Designs, IEEE International
Symposium on Circuits and Systems, May 2005. |
| Shang-Wei
Tu, Jing-Yang Jou, and Yao-Wen Chang, RLC Coupling-Aware Simulation for
On-chip Buses and Their Encoding for Delay Reduction, IEEE International
Symposium on Circuits and System, May 2005. |
| Jiun-Sheng
Huang, Shang-Wei Tu, and Jing-Yang Jou,On-Chip Bus Encoding for LC Cross-talk
Reduction, IEEE International Symposium on VLSI Design, Automation, and
Test (2005 VLSI-DAT) , April 2005. |
| Ya-Ching
Yang, Juinn-Dar Huang, Chia-Chih Yen, Che-Hua Shih, and Jing-Yang Jou,
Formal Compliance Verification of Interface Protocols, IEEE International
Symposium on VLSI Design, Automation, and Test (2005 VLSI-DAT), April
2005. |
| W. C. Tsai,
C. M. Huang, J. J. Wang, Jing-Yang Jou and C. C. Su, Design a Chip within
Half a Day: IC Design Contest in Taiwan, 2005 iNEER Conference for Engineering
Education and Research (iNEER-2005), March 2005. |
| Liang-Yu
Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, and Jing-Yang Jou,
" Communication-driven Task Binding for Multiprocessor with Latency
Insensitive Network-on-Chip", Asia and South Pacific Design Automation
Conference 2005 (ASP-DAC 2005), January 2005. |
| Tai-Ying
Jiang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, An Observability Measure
to Enhance Statement Coverage Metric for Proper Evaluation of Verification
Completeness, Asia and South Pacific Design Automation Conference 2005
(ASP-DAC 2005), January 2005. |
| Chia-Chih
Yen, and Jing-Yang Jou, "Enhancing Sequential Depth Computation with
a Branch-and-Bound Algorithm," The Ninth IEEE International High
Level Design Validation and Test Workshop (HLDVT'04), November 2004. |
Chen-Ling
Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou, "Graph
Automorphism-based Algorithm for Determining Symmetric Inputs",
International Conference on Computer Design ICCD'04, October, 2004. |
| Geeng-Wei
Lee, Chun-Yao Wang, Juinn-Dar Huang and Jing-Yang Jou, Verification on
Port Connections, Proceedings IEEE International Test Conference 2004
(ITC 2004), October 2004. |
| Shang-Wei
Tu, Jing-Yang Jou and Yao-Wen Chang, RLC Effects on Worst-case Switching
Pattern for On-chip Buses, IEEE International Symposium on Circuits and
Systems, May 2004. |
| Lily Huang,
Tai-Ying Jiang, Jing-Yang Jou and Heng-Liang Huang, An Efficient Logic
Extraction Algorithm Using Partitioning and Circuit Encoding, IEEE International
Symposium on Circuits and Systems, May 2004. |
| Yi-Wei Lin
and Jing-Yang Jou, An Efficient Approach for Hierarchical Submodule Extraction,
IEEE International Symposium on Circuits and Systems, May 2004. |
| Hue-Min
Lin, Chia-Chih Yen, Che-Hua Shih, and Jing-Yang Jou, "On Compliance
Test of On-Chip Bus for SOC", Asia and South Pacific Design Automation
Conference 2004 (ASP-DAC 2004), January 2004. |
| Shang-Wei Tu, Jing-Yang Jou,
and Yao-Wen Chang, "Layout Techniques for On-Chip Interconnect Inductance
Reduction," Asia and South Pacific Design Automation Conference 2004
(ASP-DAC 2004), January 2004. |
| Hsu-Wei
Huang, Cheng-Yeh Wang and Jing-Yang Jou, "Optimal Design of High
Fan-In Multiplexers via Mixed-Integer Nonlinear Programming", Asia
and South Pacific Design Automation Conference 2004 (ASP-DAC 2004), January
2004. |
| Chein-Wei Jen and Jing-Yang
Jou, "Nurturing Human Resources for SoC Design in Taiwan", 2003
International Conference on Engineering Education (ICEE 2003), Valencia,
Spain, July 2003. |
| Chun-Yao
Wang, Shing-Wu Tung and Jing-Yang Jou, "SOC Design Integration by
Using Automatic Interconnection Rectification", 2003 IEEE International
Symposium on Circuits and Systems (ISCAS'2003), May 2003. |
| Chih-Yang Hsu, Chien-Nan Jimmy
Liu and Jing-Yang Jou, Improved Vector Compaction for Power Estimation
with Multi-Sequence Sampling Technique, 2003 International Symposium
on VLSI Technology, Systems, and Applications, October 2003 |
| Cheng-Yeh
Wang, Ya-Chi Yang and Jing-Yang Jou, An Effective Physical Synthesis
Technique for Multiplier, 2003 International Symposium on VLSI Technology,
Systems, and Applications, October 2003. |
| I. H.-R. Jiang,
Y.-W. Chang, J.-Y. jou, and K.-Y. Chao, "Simultaneous buffer planning
and floorplanning", Asia and South Pacific Design Automation Conference
2003 (ASP-DAC 2003), January, 2003. |
| Chih-Yang
Hsu, Chien-Nan Jimmy Liu and Jing-Yang Jou, An Efficient IP-Level Power
Model for Complex Digital Circuits , Asia and South Pacific Design Automation
Conference 2003 (ASP-DAC 2003), January 2003. |
| Chun-Yao Wang,
Shing-Wu Tung and Jing-Yang Jou, An Automatic Interconnection Rectification
Technique for SoC Design Integration, Asia and South Pacific Design Automation
Conference 2003 (ASP-DAC 2003), January 2003. |
| Tai-Ying
Jiang, Chien-Nan Jimmy Liu and Jing-Yang Jou, Effective Error Diagnosis
for RTL Designs in HDLs, the Eleventh Asian Test Symposium (ATS 2002)
, Guam, USA, November 2002. |
| Chia-Chih Yen,
Kuang-Chien Chen and Jing-Yang Jou, "A Practical Approach to Cycle
Bound Estimation for Property Checking", 2002 IEEE/ACM 11th International
Workshop on Logic & Synthesis, June, 2002. |
| Chun-Yao
Wang, Shing-Wu Tung, and Jing-Yang Jou, "On Generation of The Minimum
Pattern Set for Data Path Elements in SoC Design Verification Based on
Port Order Fault Model", The Sixth IEEE International High-Level
Design Validation and Test Worshop (HLDVT'01), November 2001. |
| Chun-Yao Wang,
Shing-Wu Tung and Jing-Yang Jou, "An Improved AVPG Algorithm for
SoC Design Verification Using Port Order Fault Model", the Tenth
Asian Test Symposium (ATS 2001), Kyoto, Japan, November 2001. |
| Li-An
Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu,
and Tai-Sheng Feng, "On Placement and Routing of Wafer Scale Memory",
the 8th IEEE International Conference on Electronics, Circuits and Systems
(ICECS 2001), Malta, September 2001. |
| Hen-Ming Lin and
Jing-Yang Jou, "On Tri-state Buffer Inference in HDL Synthesis",
2001 IEEE International Symposium on Circuits and Systems (ISCAS'2001),
May 2001. |
| Chun-Yao
Wang, Shing-Wu Tung and Jing-Yang Jou, "An AVPG for SoC Design Verification
with Port Order Fault Model", 2001 IEEE International Symposium on
Circuits and Systems (ISCAS'2001), May 2001. |
| Heng-Liang Huang,
Yeong-Ren Chen, Jing-Yang Jou, and Wen-Zen Shen, "Grouped Input Power
Sensitive Transition - An Input Sequence Compaction Technique for Power
Estimation", 2001 IEEE International Symposium on Circuits and Systems
(ISCAS'2001), May 2001. |
| Chien-Nan
Jimmy Liu, Chia-Chih Yen, and Jing-Yang Jou, "Automatic Functional
Vector Generation Using the Interacting FSM Model", International
Symposium on Quality Electronic Design (ISQED 2001), March, 2001 |
| Chien-Nan Jimmy
Liu, I-Ling Chen and Jing-Yang Jou, "An Efficient Design-for-Verification
Technique for HDLs", Asia and South Pacific Design Automation Conference
2001 (ASP-DAC 2001), January, 2001. |
| Sheng-Yu
Hsu and Jing-Yang Jou, "On Topology Generation for Timing Driven
Floorplan Designs", Internatinal Conference on Chip Design Automation
(ICDA2000), August 2000. |
| Hen-Ming Lin and
Jing-Yang Jou, "On Flip-Flop Inference in HDL Synthesis", Internatinal
Conference on Chip Design Automation (ICDA2000), August 2000. |
| Chien-Nan
Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai and Hsing-Ming
Juan, "A Novel Approach for Verification Coverage Measurement in
HDL", 2000 IEEE International Symposium on Circuits and Systems (ISCAS'2000),
May, 2000. |
| Iris Hui-Ru Jiang,
S.-R. Pan,Yao-Wen Chang and Jing-Yang Jou, "Optimal Reliable Crosstalk-Driven
Interconnect Optimization", ACM/SIGDA International Symposium on
Physical Design, April 2000. |
| Heng-Liang
Huang, Jiing-Yuan Lin, Wen-Zen Shen and Jing-Yang Jou, "A New Method
for Constructing IP Level Power Model Based on Power Sensitivity",
Asia and South Pacific Design Automation Conference 2000 (ASP-DAC 2000),
January, 2000. |
| Jing-Yang Jou
and Chien-Nan Liu, "Coverage Analysis Techniques for HDL Design Validation",
The 6th Conference on Asia Pacific CHip Design Languages APCHDL'99, October,
1999. (Invited Paper) |
| Heng-Min
Lin and Jing-Yang Jou, "Correct Latch Inference in HDL Synthesis",
The 6th Conference on Asia Pacific CHip Design Languages APCHDL'99, October,
1999. |
| Chih-Chun Ma,
Heng-Min Lin and Jing-Yang Jou, "On Address Generation for Embedded
System Using Scheduling Techniques", The 6th Conference on Asia Pacific
CHip Design Languages APCHDL'99, October, 1999. |
| Chien-Nan
Jimmy Liu and Jing-Yang Jou, "An Efficient Functional Coverage Metric
for HDL Using the Semantic Finite State Machine Model", International
Conference on Computer Design ICCD'99, October, 1999. |
| Heng-Min Lin and
Jing-Yang Jou,"Computing Minimum Feedback Vertex Sets by Contraction
Operations and its Applications on CAD", International Conference
on Computer Design ICCD'99, October, 1999. |
| Hui-Ru
Jiang, Jing-Yang Jou and Yao-Wen Chang, "Noise-Constrained Performance
Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian
Relaxation", 36th Design Automation Conference (DAC'99), June 1999. |
| Michael Chen,
Jing-Yang Jou and Heng-Min Lin, "An Efficient Algorithm for the Multiple
Constant Multiplication Problem", 1999 International Symposium on
VLSI Technology, Systems, and Applications, June 1999. |
| Jiann-Horng
Lin, Jing-Yang Jou and Hui-Ru Jiang, "Hierarchical Floorplan Design
on the Internet", Asia and South Pacific Design Automation Conference
1999 (ASP-DAC'99), January 1999. |
| Shing-Wu Tung
and Jing-Yang Jou, "Verification Pattern Generation for Core-Based
Design Using Port Order Fault Model", The Seventh Asian Test Symposium,
December 1998. |
| Chien-Nan
Liu and Jing-Yang Jou, "A FSM Extractor for HDL Description",
Asia-Pacific Conference on Hardware Description Languages APCHDL'98, June,
1998. |
| Jie-Hong Jiang,
Jing-Yang Jou and Juinn-Dar Huang, "Compatible Class Encoding in
Hyper-Function Decomposition for FPGA Synthesis", 35th Design Automation
Conference (DAC'98), June 1998. |
| Jiing-Yuan
Lin, Wen-Zen Shen and Jing-Yang Jou, "A Power Modeling and Characterization
Method for Macrocells Using Structure Information", Proceedings of
International Conference on Computer-Aided Design, November 1997. |
| Jing-Yang Jou
and Ming-Chang Nien, "Power Driven Partial Scan", International
Conference on Computer Design ICCD'97, October, 1997. |
| Shing-Wu
Tung and Jing-Yang Jou, "Library Coherence Checking Using Port Order
Fault Model", Asia-Pacific Conference on Hardware Description Languages
APCHDL'97, August, 1997. |
| C. L. Lee, J.-Y.
Jou, Cs. S. Lin, J. E. Chen, C. W. Wu, K. J. Lee and C. C. Su, "A
Joint Project to Develop a VLSI Testing and Design-for-Testability Course
for Universities in Taiwan", ICEE, August 1997. |
| Jyh-Mou
Tseng and Jing-Yang Jou, "A Power-Driven Two-Level Logic Optimizer",
1997 Asia and South Pacific Design Automation Conference (ASP-DAC'97),
January, 1997. |
| Jie-Hong Jiang,
Jing-Yang Jou, Juinn-Dar Huang and Jung-Shian Wei, "BDD Based Lamada
Set Selection in Roth-Karp Decomposition for LUT Architecture", 1997
Asia and South Pacific Design Automation Conference (ASP-DAC'97), January,
1997. |
| Juinn-Dar
Huang, Jing-Yang Jou and Wen-Zen Shen, "An Iterative Area/Performance
Trade-Off Algorithm for LUT-Based FPGA Technology Mapping", Proceedings
of International Conference on Computer-Aided Design, November 1996. |
| Jiing-Yuan Lin,
wen-Zen Shen and Jing-Yang Jou, "A Power Modeling and Characterization
Method for the CMOS Standard Cell Library", Proceedings of International
Conference on Computer-Aided Design, November 1996. |
| Li-Ren
Huang, Jing-Yang Jou, and Sy-Yen Kuo, "An Efficient PRPG Strategy
by Utilizing Essential Faults", The Fifth Asian Test Symposium, November
1996. |
| Li-Ren Huang,
Jing-Yang Jou, and Sy-Yen Kuo, "Easily Testable Data Path Allocation
Using Input/Output Registers", The Fifth Asian Test Symposium, November
1996. |
| Juinn-Dar
Huang, Jing-Yang Jou, and Wen-Zen Shen, "Compatible Class Encoding
in Roth-Karp Decomposition for Two-Output LUT Architecture", Proceedings
of International Conference on Computer-Aided Design, November 1995. |
| Jing-Yang Jou,
"An Effective BIST Design for PLA", The Fourth Asian Test Symposium,
November 1995. |
| Jing-Yang
Jou, and K.-T. Cheng, "Timing-Driven Partial Scan", Proceedings
of International Conference on Computer-Aided Design, November 1991. |
| K.-T. Cheng, J.
Dussault, J. J. Fishburn, Jing-Yang Jou, M. C. Lega, and M. M. Tong, "Behavioral
and Logic Synthesis for Performance and Testability", Proceedings
of International Symposium on IC Design, Manufacture & Applications,
Singapore 1991. |
| K.-T.
Cheng, and Jing-Yang Jou, "A Single-State-Transition Fault Model
for Sequential Machines", Distinguished Paper, Proceedings of International
Conference on Computer-Aided Design, November 1990. |
| K.-T. Cheng, and
Jing-Yang Jou, "Functional Test Generation of Finite State Machines",
Proceedings of International Test Conference, September 1990. |
| R.
Ernst, S. Sutarwala, Jing-Yang Jou, and M. Tong, "Simulation-Based
Verification of Register-Transfer Level Behavioral Synthesis Tools",
Proceedings of EDAC '90, March 1990. |
| K.-T. Cheng, and
Jing-Yang Jou, "Functional Test Generation of Finite State Machines",
Proceedings of AT&T Conference on Electronic Testing, May 1990. |
| Jing-Yang
Jou, S. Rothweiler, R. Ernst, S. Sutarwala and A. Prabhu, "BESTMAP:
Behavioral Synthesis From C", Proceedings of International Workshop
on Logic Synthesis, MCNC, May 1989. |
| C.-L. Wey, S.-M.
Chang, and Jing-Yang Jou, "OPAM: An Efficient Output Phase Assignment
for Multi-level Logic Minimization", ICCD'89, October 1989. |
| Jing-Yang
Jou, and Tonysheng Lin, "A High-Level Fault Modeling Technique Using
CONES", Proceedings of 32nd Midwest Symposium on Circuits and Systems,
August 1989. |
| R. Ernst, S. Sutarwala,
and Jing-Yang Jou, "TSG - a Test System Generator for Debugging and
Regression Test of High-Level Behavioral Synthesis Tools", Proceedings
of ITC'89, September 1989. |
| C.-L.
Wey, S.-M. Chang, and Jing-Yang Jou, "An Efficient Output Phase Assignment
for Multi-level Logic Minimization", Proceedings of International
Workshop on Logic Synthesis, MCNC, May 1989. |
| Jing-Yang Jou,
"A Testable PLA Design with Low Overhead and Ease of Test Generation,"
Proceedings of ICCD'88, October 1988. |
| Jing-Yang
Jou, and Tonysheng Lin, "A High-Level Fault Modeling Technique Using
CONES", Proceedings of AT&T Conference on Electronic Testing,
October 1988. |
| Wu-Tung Cheng,
and Jing-Yang Jou, "A Hierarchical Sequential Test Generator",
Proceedings of 26th Annual Allerton Conference on Communications, Control,
and Computing, September 1988. |
| Jing-Yang
Jou, and J. A. Abraham, "Fault-Tolerant Algorithms and Architectures
for Real time Signal Processing," Proceedings of the 1988 International
Conference on parallel Processing, August, 1988. |
| Ruey-Sing Wei,
Steven Rothweiler, and Jing-Yang Jou, "BECOME: Behavior Level Circuit
Synthesis Based on Structure Mapping," Proceedings of 25th ACM/IEEE
Design Automation Conference, June 1988. |
| Wu-Tung
Cheng, and Jing-Yang Jou, "Hierarchical Sequential Test Generation
in High-Level Synthesis Environment", Proceedings of AT&T Conference
on Electronic Testing, October 1987. |
| Jing-Yang Jou,
and J. A. Abraham, "Fault-Tolerant FFT Networks", the Fifteenth
International Symposium on Fault-Tolerant Computing, Ann Arbor, June 1985. |
| K.
Hua, Jing-Yang Jou, and J. A. Abraham, "Built-In Tests for VLSI Finite-State
Machines," Tutorial: VLSI Testing & Validation Technique, Edited
by Hassan K. Reghbati, IEEE Computer Society Press, 1985. |
| Jing-Yang Jou,
and J. A. Abraham, "Fault Tolerant Matrix Operations on Multiple
Processor Systems Using Weighted Checksums," SPIE Proceedings Vol.
495, Real Time Signal Processing VII, August 1984. |
| K.
Hua, Jing-Yang Jou, and J. A. Abraham, "Built-In Tests for VLSI Finite-State
Machines," Proceedings of the 14th Annual International Conference
on Fault-Tolerant Computing. Orlando, Florida, June 1984. |
